Samsung Claims First with In-Memory MRAM – EE Times
Samsung today announced an MRAM innovation, claiming the world’s first in-memory computing based on MRAM capable of performing both data storage and data computing within a single memory network. The company claims its MRAR array chip is the next step to realizing low-power AI chips.
Use of in-memory computing architectures has increased over the years because of its ability to crunch data at the edge, which can in turn reduce the amount of data movement and network latency. Samsung’s renewed focus on in-memory computing, however, stems from MRAR’s low-resistant nature, which ordinarily limits its ability to reduce power consumption when used in standard in-memory architecture.
Samsung claims its own MRAR array chip eliminates this issue, however, with what it calls ‘resistance sum’ in-memory computing architecture.
Several in-memory computing architectures traditionally rely on crossbar arrays of non-volatile memories, which execute multiply-accumulate operations in an analog manner, according to Samsung. But the challenge is creating a crossbar array capable of spin-transer-torque MRAM.
“[MRAM offers] practical advantages such as endurance and large-scale commercialization. The difficulty stems from the low resistance of MRAM, which would result in large power consumption in a conventional crossbar array that uses current summation for analogue multiply–accumulate operations,” Samsung said in its paper published by Nature.
Samsung’s research team claims they’ve successfully developed an MRAM array chip with a 64 x 64 crossbar array based on MRAM cells that overcomes the low-resistance issue with an architecture “that uses resistance summation for analogue multiply–accumulate operations,” according to the paper.
The company integrated its MRAM array chip with readout electronics in 28nm complementary metal-oxide-semiconductor technology.
Samsung’s research team, led by Samsung Advanced Institute of Technology (SAIT) in collaboration with the company’s Electronics Foundry Business and Semiconductor R&D Center, says they’ve put its MRAM chip to the test with several AI-based instances. The MRAM-based in-memory computing chip achieved 98% accuracy in classification of hand-written digits and 93% accuracy in detecting faces from scenes, according to Samsung.
Beyond in-memory computing, Samsung is hoping to extend its MRAM array chip to biological neuronal network use cases, as well. The company has set its sights on neuromorphic electronics research and recently released a paper outlining its vision of neuromorphic chips on Sept. 26, 2021. The paper unveils Samsung’s notion of reverse engineering the brain onto a memory chip, which would essentially allow a neuromorphic chip to emulate a human brain with a ‘copy and paste’ approach.
“[Samsung] envisions to create a memory chip that approximates the unique computing traits of the brain — low power, facile learning, adaptation to environment, and even autonomy and cognition — that have been beyond the reach of current technology.”
With this type of neural technology, AI models could go beyond current data processing limitations, becoming increasingly flexibility and capable of producing more accurate algorithms. Neuromorphic engineering, however, also introduces its own set of hurdles. Neuromorphic chips would require development of their own classification of memory and storage beyond what’s currently available. These chips would also likely require a whole new programming language with specialized encoding and processing concepts.
Samsung remains hopeful, however, because of MRAM’s potential to work similarly to neural synapses.
“In-memory computing draws similarity to the brain in the sense that in the brain, computing also occurs within the network of biological memories, or synapses, the points where neurons touch one another,” said Dr. Seungchul Jung, staff researcher at SAIT. “In fact, while the computing performed by our MRAM network for now has a different purpose from the computing performed by the brain, such solid-state memory network may in the future be used as a platform to mimic the brain by modeling the brain’s synapse connectivity.”
Stefani Munoz is associate editor of EE Times. Prior to joining EE Times, Stefani was an editor for TechTarget and covered a host of topics around IT virtualization trends and VMware technologies.
At TRW, we had a multiport RAM chip with on-board address generators decades ago.
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